Test and Measurement Connectors 8 pins

JTAG Boundary Scan Connector

JTAG boundary scan (IEEE 1149.1) uses a 14-pin or 20-pin header to test PCB interconnects, program FPGAs, and debug embedded processors by shifting data through boundary scan cells in each IC.

// connector diagram 8 pins

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// Specifications

Standard

IEEE 1149.1 JTAG

Pin Count

14-pin or 20-pin 2.54mm pitch

Signals

TDI TDO TCK TMS TRST optional

Speed

Up to 30 MHz TCK

Use Case

PCB boundary scan test FPGA programming in-circuit debug

Tools

Segger J-Link Xilinx Platform Cable Altera USB Blaster

// Pin Reference Table

Pin	Name	Function	Type
1	VCC	Target supply voltage reference	PWR
2	GND	Ground	GND
3	TCK	Test clock	BUS
4	TDI	Test data input	BUS
5	TDO	Test data output	BUS
6	TMS	Test mode select	BUS
7	TRST	Test reset optional	I/O
8	nSRST	System reset optional	I/O

JTAG boundary scan (IEEE 1149.1) uses a 14-pin or 20-pin header to test PCB interconnects, program FPGAs, and debug embedded processors by shifting data through boundary scan cells in each IC.